This invention relates, in general, to a process for fabricating a semiconductor device, and more particularly, to a process for a lithographically defining patterned features in a semiconductor device.
In order to build faster and more complex integrated circuits, semiconductor manufacturers have increased the number of components in the integrated circuit, while reducing the overall size of the circuit. The small circuit size requires device components be defined to smaller and smaller dimensions. In addition, the small circuit size requires multiple overlying conductive layers to electrically interconnect the vast number of components within the integrated circuit. To achieve high performance levels, the electrical interconnects must be fabricated in dense arrays with minimal spacing between each conductive lead. As the need to fabricate numerous electrical interconnect leads at very high densities increases, demands are placed on photolithographic technology to accurately transfer lithographic patterns into underlying conductive layers.
Conventional photolithography involves the formation of a lithographic pattern on an underlying layer to which the lithographic pattern is to be transferred. Typically, in an optical process, a layer of photoresist is spin-coated onto an underlying layer. The photoresist is exposed to a pre-selected wavelength of light to cause a photo-sensitive chemical reaction to occur in the photoresist. After exposure, the photoresist is developed to remove portions of the photoresist and to leave a pattern on the underlying layer. The pattern is then transferred into the underlying layer by performing an etching process using the patterned photoresist as an etching mask.
As the feature size of the lithographic pattern is reduced, inaccuracies in the pattern transfer process can arise from optical limitations inherent in the lithographic process. For example, during the formation of metal leads, light reflection from the surface of the underlying metal layer can cause distortions in the developed photoresist patterns.
To control the reflection of light from the metal surface, conventional photolithographic processes employ an anti-reflective coating process (ARC) that is positioned between the underlying layer and the photoresist. Anti-reflective coatings are conventionally made of various materials, including organic and inorganic materials. For example, inorganic materials conventionally employed for ARCs includes silicon nitride, silicon oxynitride, titanium nitride, silicon carbide, and the like. Organic materials conventionally employed for ARCs include spin-on polyamides and polysulfones. The effective use of an ARC enables patterning, and alignment without reflective interference from the surface of the underlying layer. Reduction in light reflection improves both line width reproduction accuracy and mask alignment. These are critical process parameters that are necessary to achieve fine line conductive patterns at high densities. The use of an ARC is particularly beneficial when forming a via or contact hole over a stepped area. In these processes, a dielectric layer must be etched that has been deposited on a gate electrode overlying a semiconductor substrate. Light reflection from the gate electrode can distort the pattern geometry of the opening.
Despite the development and use of ARCs, conventional photolithographic techniques are a limiting factor in the reduction of feature sizes in integrated circuit devices. Accordingly, a need exists for materials that have the requisite optical properties for use as a ARC, and that enable accurate control of line width of conductive features. An important aspect of the ARC is that it withstands the etching processes used to transfer patterns from the photoresist into underlying conductive materials. Additionally, the ARC must have a chemical composition, such that it can be removed without damaging underlying patterned features. Accordingly, a need exists for further development of ARC materials that can provide the needed enhancement of conventional photolithographic pattern transfer processes.
The present invention is for a process for fabricating a semiconductor device that includes the formation of an anti-reflective layer that is resistant to etching processes used to remove exposed portions of underlying layers. In a preferred embodiment of the invention, the anti-reflective layer includes a silicon-rich silicon nitride material. The silicon-rich silicon nitride material is not reactive with etchants used to remove dielectric materials that form portions of pattern features in an integrated circuit device. By incorporating excess silicon, the silicon nitride material can be adjusted to exhibit a desired refractive index and absorption coefficient. Additionally, the silicon-rich silicon nitride is resistant to etchants that react with dielectric materials, such as silicon oxide. Additionally, the silicon-rich silicon nitride is resistant to etchants that are reactive with semiconductor materials, such as single-crystal silicon and polycrystalline silicon.
In one embodiment, a semiconductor substrate is provided and a device layer is formed on the semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. An anti-reflective layer that includes a silicon-rich silicon nitride layer is plasma deposited onto the device layer.